Cadence XCELIUM v23.03.002



Cadence验证套件针对Arm 设计进行了优化:

JasperGold® 形式验证平台:实现IP和子系统验证,包括Arm AMBA® 协议的形式化验证
Xcelium® 并行逻辑仿真器:提供经过产品验证的多核仿真器,加速SoC研发和其余Arm的设计验证
Palladium® Z1企业级仿真平台:包括基于Arm 快速模型(Fast Model)集成的Hybrid技术,操作系统启动最快提升50倍,基于应用软件的软件运行速度最快提升10倍,并利用动态功耗分析技术实现功耗快速预估
Protium™ S1 FPGA原型平台:与Palladium Z1企业级仿真平台集成使用,并可与Arm DS-5集成来进行流片前嵌入式软件的调试
vManager™规划与度量工具:为JasperGold平台、Xcelium仿真、Palladium Z1平台和Cadence VIP解决方案提供度量验证,实现Arm系统级芯片的验证收敛
Perspec™ 系统验证工具:结合面向Armv8架构设计的PSLib,提供软件驱动的用例验证,较传统验证激励开发效率最高提升10倍
Indago™ 调试平台:可对RTL设计、验证环境和嵌入式软件进行调试, 并支持基于Arm CPU的软硬件协同调试
Cadence验证工作台:与Arm Socrates™封装 Armv8 IP和VIP相结合,实现快速的SoC集成和UVM测试环境的搭建
Cadence互联工作台:可与Xcelium仿真器、Palladium Z1平台和Cadence验证IP同时使用,对基于Arm CoreLink™ 互联IP的系统进行快速的性能分析与验证
验证IP组合:实现包括Arm AMBA互联在内的IP和SoC验证,支持Xcelium仿真器、JasperGold平台和Palladium Z1平台

Cadence XCELIUM version 23.x| 6.8 Gb

Cadence Design Systems, Inc. , the leader in global electronic design innovation, is pleased to announce the availability of XCELIUM Main 23.03.001 (Base) is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.

Cadence’s Xcelium Logic Simulation provides best-in-class core engine performance for SystemVerilog, VHDL, mixed-signal, low power, and x-propagation. It supports both single-core and multi-core simulation, incremental and parallel build, and save/restart with dynamic test reload. The Xcelium Logic Simulator has been deployed by a majority of top semiconductor companies, and a majority of top companies in the hyperscale, automotive and consumer electronics segments. Using computational software and a proprietary machine learning technology that directly interfaces to the simulation kernel, Xcelium learns iteratively over an entire simulation regression. It analyzes patterns hidden in the verification environment and guides the Xcelium randomization kernel on subsequent regression runs to achieve matching coverage with reduced simulation cycles. Xcelium is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.

Are long DFT simulations posing a big challenge to meet your tight project schedules? We have a solution to accelerate the long running DFT tests. Watch this video to know how easy it is to set-up Xcelium Multi-Core to get up to 5X acceleration for a variety of DFT use cases ranging from serial and parallel ATPG to MBIST and LBIST
Cadence is a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world’s most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.

Product: Cadence XCELIUM
Version: 23.03.x (XCELIUMMAIN) Base
Supported Architectures: x86_64
Website Home Page :
Languages Supported: english
System Requirements: Linux *
Size: 6.8 Gb


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