Mentor Graphics Corporation，西门子公司，很高兴地宣布Questa正式2021.1可用性。这个解决方案可以发现模糊的bug，通过详尽的分析增加设计的信心，在模拟测试环境可用之前，还可以通过针对难以完成的验证任务来提高生产率和功能验证质量。
– cdc promote constraint -修改指定cdc约束的提升属性的新指令。
– reset_as_data -异步设置或复位信号连接到数据引脚。
– case_small – case语句的case项更少。
– comment_density_low -设计文件的注释密度小于指定的限制。
– func_arg_array_constrained – function参数是一个约束数组。
– net_decl_with_assign – net在同一语句中声明和赋值
– package_disallowed -不允许使用指定的包。
– pragma_disallowed -不允许使用指定的pragma。
– reg_reset_value_disallowed -寄存器被分配了一个重置值，这是不允许的。
The Questa verification solution from Siemens EDA, a part of Siemens Digital Industries Software, continues to evolve in response to the growing complexity of SoC designs. Besides the sheer size of designs, the inclusion of multiple embedded processors and advanced interconnect systems, increasing software content and the configurability required by multi-platform based designs require a functional verification solution that unifies a broad arsenal of verification solutions.
Questa lets you apply CDC verification, formal verification, mixed-signal verification, portable stimulus, and other powerful technologies to maximize the effectiveness of your verification at the block- and subsystem-level so your system-level verification can focus on system-level functionality, including software, without having to worry about lower-level bugs taking away from your productivity. No one wants to compromise product quality. However, time-to market pressures dominate SoC projects. To deliver quality within schedule requires improving the time to achieve coverage and quality goals and improving debug productivity.
Questa Formal Apps statically analyze a design’s behavior with respect to a given set of properties; then exhaustively explore all possible input sequences in a breadth-first search manner. This uncovers design errors that would otherwise be missed or are impractical to find with simulation-based methods.
Questa Formal Apps boost verification efficiency and design quality by exhaustively addressing verification tasks that are difficult to complete with traditional methods, and they don’t require formal or assertion-based verification experience.
Properties are synthesized from a combination of automatic RTL design analysis and a high-level specification of design intent. The generated properties are then exhaustively verified with formal analysis engines.
The Questa Formal App suite includes applications to address tasks such as: static and conditional connectivity checking, secure path integrity checking, unreachable code identification, X-state propagation, state-space analysis, and register verification. Additionally, the Questa Sequential Logic Equivalence Checking (SLEC) App uses formal methods to perform exhaustive comparisons between inputs to reveal any behavioral discrepancies that could arise in clock gating, ECO integration, re-pipelining, or fault mitigation logic.
Product: Mentor Questa Formal
Supported Architectures: x64
Website Home Page : https://eda.sw.siemens.com/
Languages Supported: english
System Requirements: PC *
Size: 1.29 Gb